Intel Compute Stack Enables LEO For Nova Lake, Introduces Intel Portable ISA "PISA"

Released today was the Intel Compute Runtime 26.35.39758.10 update for Windows and Linux systems. With this updated OpenCL and Level Zero GPU compute driver stack comes some exciting updates for this monthly feature update.

A number of new features were merged for this Intel Compute Runtime update. There is enabling host function-based external semaphores, a new hook for applying OpenVINO-related AIL, Sysman gained an implementation of Info Log APIs, Sysman also added initial composite temperature support, and initial support for reading the memory Vendor ID (VID) in the Compute Runtime. In the Linux-specific code is now enabling the Linux kernel driver integration to wait for event host synchronization.

On the OpenCL side is support for the cl_khr_spirv_queries extension, cl_khr_command_buffer infrastructure, and other changes for the new LEO driver. OpenCL LEO debuted earlier this year as an experimental OpenCL implementation being built atop the Level Zero APIs rather than OpenCL direct-to-hardware with their existing OpenCL driver. OpenCL has continued improving with each succeeding release.

Now with the Intel Compute Runtime 26.35.39758.10 is enabling the OpenCL LEO driver by default for upcoming Nova Lake S processors on Linux. Finally, OpenCL LEO is seeing enablement by default beginning with next-gen NVL-S processors as a very exciting development. For existing Intel iGPUs and dGPUs the LEO driver is still treated as experimental.

Also significant is adding initial Intel Compute Runtime support for the PISA format. Intel PISA is the Portable ISA specification for Intel GPUs as a programming model and ISA for general purpose parallel programming. Per the v0.1 documentation, the Intel PISA goals include:

- Provide a stable, portable ISA for compilers targeting Intel GPUs

- Provide “close-to-the-metal” performance comparable to native machine ISA code

- Facilitate advanced programming support such as hand-written libraries and inline assembly

Intel PISA appears to be akin to NVIDIA's NVPTX. Intel has also been working toward upstreaming a PISA GPU back-end within the LLVM compiler stack.

Crescent Island enablement continues with now enabling defer backing and other changes.

The new Intel Compute Runtime release can be downloaded at GitHub.