China Develops GAA Transistors That Enable 3nm Node-Like Performance On DUV Lithography, But MEOL Constraints Only Provide A Path To 5nm Node-Equivalent Performance

Despite the fact that American export controls continue to restrict China to the older DUV lithography tech, the Asian giant has been using innovative techniques to extract the maximum possible juice from these older machines, and the Chinese Academy of Sciences might just have carved out a viable pathway to 3nm-like performance - albeit constrained by Middle-End-Of-Line (MEOL) realities - by developing new GAA transistors.

The Chinese Academy of Sciences (CAS) has developed new gate-all-around (GAA) transistors with on-off ratios above 500,000, unlocking 3nm-equivalent performance

The Chinese Academy of Sciences has just revealed a breakthrough transistor architecture that can theoretically unlock 3nm-like performance from China's DUV lithography machines.

For the benefit of those who might not be aware, transistors are microscopic electrical switches that turn electric current on and off in rapid succession, mimicking the binary 1s and 0s that form the basis of computing. A typical chip contains billions of these transistors.

Older FinFET transistors are typically shaped like a fin sticking up. GAA transistors, however, wrap around a given electrical channel, and offer much better control over the flow of electric current. Think of these transistors as akin to squeezing a hose pipe with your entire hand rather than pinching with just two fingers.

The CAS has now developed GAA transistors that offer on-off ratios above 500,000, which means that the quantum of electric current flowing through when the switch is on is 500,000x greater than what flows when it is off, exhibiting excellent electrical control and nearly eliminating leakage current.

What's more, the CAS claims that it made these these transistors using DUV machines. Ordinarily, the light emitted from DUV lithography is not sufficient to print 3nm-level electrical circuits. Even so, multi-patterning - where etching steps are repeated to achieve progressively finer circuits - and immersion DUV - which uses ultra-pure water to magnify the laser's resolution - can be used to print 7nm-level circuits. The CAS, however, is now claiming that its new transistors unlock a pathway to 3nm-equivalent performance.

In chip fabrication, Front-End-Of-The-Line (FEOL) process deals with the creation of transistors. Given the excellent electrical controls of these new GAA transistors from CAS, it is possible to relax the fin pitch - that is, space transistors a bit more loosely while achieving the same performance as that of a denser FinFET transistor architecture.

The Middle-End-Of-The-Line (MEOL) process deals with metal connects that link each transistor to the wider circuit, and require etching very precise trenches or holes and filling them with metal. The Back-End-Of-The-Line (BEOL) process deals with all the higher metal wiring layers that connect everything together across the chip. Here, M0 is the very lowest metal layer, and the hardest to fabricate, especially as it’s the finest and closest to the transistors. According to the semi expert 'aog T,' the "MEOL contact trench/ hole and BEOL M0" are two of the most persistent challenges for SMIC, especially as these processes can't benefit from improvements to the GAA transistor itself. What's more, even the poly pitch - the spacing between gates - is also determined by MEOL complexity.

Even so, once you are able to relax the fin pitch, SMIC can shrink the logic cell height by going from a 5-track M0 to a 4-track one, unlocking "G57H198" or "G54H198" logic cells (density of around 137.8 MTr/mm²), which is roughly equal to the density offered by TSMC's 5nm node. Basically, SMIC can pack things a bit more densely by using the new GAA transistors and making the logic cells shorter, even if their middle and early wiring layers are still struggling, potentially unlocking 5nm-equivalent performance.

Of course, Huawei and SMIC are pursuing other architectural improvements simultaneously. As we noted earlier today, Huawei has just teased its next-gen Ascend 960 chips, leveraging LogicFolding to accelerate the launch cadence for the Ascend 960 from Q3 2027 to Q1 2027. For the benefit of those who might not be aware, LogicFolding stacks logic circuits vertically, increasing the compute density even as individual circuits might not pack transistors as densely. This approach also shortens signal paths, and leverages fine-pitch vertical interconnects (down to the micron scale) to allow separate active silicon tiers to operate functionally as a monolithic unit.